3-bit R-2R Digital to Analog Converter with Better INL&DNL
Ankit Upadhyay1, Rajanikant M. Soni2
1Ankit Upadhyay, Electronics and Communication Department College LCIT, Bhandu and Gujarat Technological University, Ahmedabad, India.
2Rajanikat M. Soni, Electronics and Communication, Gujarat Technological University, Mehsana, India.
Manuscript received on January 21, 2013. | Revised Manuscript received on February 11, 2013. | Manuscript published on February 28, 2013. | PP: 401-403 | Volume-2 Issue-3, February 2013.  | Retrieval Number: C1157022313/2013©BEIESP

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper analysis of 3-bit R-2R ladder DAC proposed with most of the specification in the last decade has been done. All analysis have been supported by simulations results. To carry out the simulations Eldo spice, IC Station and Design architect from Mentor Graphics Tools is used. For all about Pre Layout simulation has been realized using (0.35um) CMOS process Technology.
Keywords: Digital-to-analog converters(DAC),R-2R ladder network., DNL,INL.