Front Design and Implementation of High Speed Hybrid Dual D-Fifo-Ff (Flip-Flop) Synchronizer Using Verilog
S. K Ganesh Kumar Pedapudi1, B.Rajasekar2
1S. K Ganesh Kumar Pedapudi, Research Scholar, Department of ECE, Sathyabama Institute of Science and Technology, Chennai (Tamil Nadu), India.
2Dr. B. Rajasekar, Associate Professor, Department of ECE, Sathyabama Institute of Science and Technology, Chennai (Tamil Nadu), India.
Manuscript received on 25 May 2019 | Revised Manuscript received on 03 June 2019 | Manuscript Published on 22 June 2019 | PP: 198-205 | Volume-8 Issue-3S, February 2019 | Retrieval Number: C10410283S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Phase Measurement in certain applications where signal and its related information needs to be sustained synchronously results in to measure different phases for the application intended. Such orthodox systems would emphasize on measurements of time and phases implementing as an original mixed signal approach. This imparts uncertainty of the different phases in regards to recovered signals. To initiate such intricacies, specifically related to phase shift changes in FPGA, we impart the specific design logic core such as synchronizer and digital phase detector module for phase measurement system providing higher resolution and better precision in specific range of few Pico seconds. In this design scenario we estimate the design of the synchronizer and phase detector using Dual D-flip flops such module level modifications would arise systematic sampling over the phase detected signal. Our design with Dual D-FF would suffice the estimation of the model for customized model for Synchronizer resulting in Power and Area for respective test benchmark and has been compared and tabulated with existing system synchronizer. The design is estimated with mathematical modeling to emphasize the correct scenario for the synchronized values observed and its phase detection using Dual D flip flop. Our design methodology is implemented using Verilog HDL using HDL designer series and modelled for its netlist analysis using Xilinx Spartan 3 XCS 200TQ-144.
Keywords: Design High Speed Measurement.
Scope of the Article: High Speed Networks