Design and Implementation of Viterbi Encoder and Decoder using FPGA
Chitra M.1, A. R. Ashwath2, Roopa M.3
1Chitra M., Electronics and communication, Dayananda sagar college of Engineering, Bangalore, India.
2Dr. A. R. Ashwath, Telecommunication Engineering, Dayanada sagar college of engineering, Bangalore, India.
3Roopa M., Electronics and communication Engineering, Dayanada sagar college of engineering, Bangalore, India.
Manuscript received on may 17, 2012. | Revised Manuscript received on June 13, 2012. | Manuscript published on June 30, 2012. | PP: 100-106 | Volume-1 Issue-5, June 2012 | Retrieval Number: C0222021312/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we present an implementation of the Viterbi algorithm using the Hardware Description Language and Implemented on FPGA. We begin with a description of the algorithm. Included are aspects of design specifications that must be considered when implementing the Viterbi algorithm as well as properties of Verilog HDL that can be used to simplify or optimize the algorithm. Finally, we evaluate the performance of the Viterbi algorithm implemented on FPGA.
Keywords: HDL-Hardware Descriptive Language, FPGA- Field Programmable Gate Array.