Low Power CMOS Design of an SRAM Cell with Sense Amplifier
Swati Anand Dwived
Swati Anand Dwivedi, Electronics & Communication, R.G.P.V./ S.R.I.T. Jabalpur, India.
Manuscript received on January 17, 2012. | Revised Manuscript received on February 05, 2012. | Manuscript published on February 29, 2012. | PP: 157-160 | Volume-1 Issue-3, February 2012. | Retrieval Number: C0213021312/2011©BEIESP
Open Access | Ethics and Policies | Cite
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Power dissipation and switching delay are the focusing point in any circuit used in memory. It is required to design a circuit having low power dissipation and high switching speed in order to meet the current requirements. Reduction in power can be done by several methods. Here low power current sensing scheme for CMOS SRAM is presented in this paper. Large bit-line capacitance is one of the main bottlenecks to the performance of on-chip caches. New sense amplifier techniques need to explicitly address this challenge. The current sense amplifier senses the cell current directly and shows a speed improvement of 17-20% for 128 memory cells as compared to the conventional voltage mode sense amplifier.
Keywords: CMOS, SRAM, Sense Amplifier, Swithching delay, VLSI