High throughput and area efficient FPGA Implementation of AES algorithm
P. B. Mane1, A. O. Mulani2

1P. B. Mane, Department of Electronics & Telecommunication, AISSMS Inst. of Information Technology, Pune (M.H), India
2A. O. Mulani, Department of Electronics & Telecommunication, SKN Sinhgad College of Engg., Pandharpur (M.H), India

Manuscript received on 18 April 2019 | Revised Manuscript received on 25 April 2019 | Manuscript published on 30 April 2019 | PP: 519-523 | Volume-8 Issue-4, April 2019 | Retrieval Number: B5573128218/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Now a days, digital data is very easy to process but it permits unauthorized consumers to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the best and commonly used symmetric key cryptographic algorithm. Main aim of this article is to implement fast and safe AES algorithm on reconfigurable platform. AES algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.
Keywords: AES, Cryptography, FPGA, VLSI, System Generator

Scope of the Article: Cryptography and Applied Mathematics