Design and Implementation of an N bit Vedic Multiplier using DCT
Shazeeda1, Monika Sharma D2

1Shazeeda, School Of Electrical & Electronic Engineering, Universiti Sains Malaysia (USM), Engineering Campus, Seberang Perai Selatan, Nibong Tebal, Penang Malaysia.
2Monika Sharma D, Department of Electronics and Communication, SJM Institute of Technology (SJMIT), Chitradurga (Karnataka), India.

Manuscript received on 15 December 2015 | Revised Manuscript received on 25 December 2015 | Manuscript Published on 30 December 2015 | PP: 34-41 | Volume-5 Issue-2, December 2015 | Retrieval Number: B4324125215/15©BEIESP
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Abstract: One of the basic and fundamental functions in arithmetic operation is multiplication. Many of the application such as convolution and Fourier transform in digital signal processing, in microprocessors multiplication is very frequently used operation. In this paper we propose a fast multiplication method based on ancient Indian Vedic mathematics. The Vedic mathematics demonstrate the unified structure of mathematics by the 16 formulas. The generalized multiplication formula which is applicable in all cases is called Urdhava Triyakbhyam. In this paper we designed a Vedic multiplier in VHDL (Very High Speed Integrated circuit Hardware Description Language) and synthesis is done in Xilinx ISE series. The combinational delay of this multiplier is estimated and compared with that of Wallace tree multiplier. The results showed a significant improvement in the propagation delay. The Vedic multiplier showed a propagation delay of 10.295 ns and 25.236 ns for 4 and 8 bit multiplication, respectively.
Keywords: Vedic Multiplier, Wallace Tree Multiplier, Urdhva Tiryakbhyam, Discrete Cosine Transform.

Scope of the Article: Discrete Optimization