High Performance Energy Efficient Computation Elements of Processing Unit
Dhanabal Rengasamy1, Ramakrishnan V. N2

1Dhanabal Rengasamy*, Assistant Professor, DMNE, SENSE, Vellore Institute of Technology, Vellore (Tamil Nadu) India.
2Ramakrishnan V. N., Associate Professor, DMNE, SENSE, Vellore Institute of Technology, Vellore (Tamil Nadu) India
Manuscript received on November 22, 2019. | Revised Manuscript received on December 15, 2019. | Manuscript published on December 30, 2019. | PP: 2450-2455 | Volume-9 Issue-2, December, 2019. | Retrieval Number:  B3964129219/2019©BEIESP | DOI: 10.35940/ijeat.B3964.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In our manuscript, various circuits for arithmetic summation are compared. Cadence 90nm technology and Quartus II EP2C20F484C7 are used for implementation of design. Logic gate-based adders, PFCA, TG and HSD technique-based adders characteristics are analyzed. Y finding is PFCA with 10T transistor performs slightly efficient compare to its counterpart. Exclusive OR-NOR design is optimum for least delay Adders for high performance energy efficient processing unit.
Keywords: Adders, Multipliers, Power Dissipation, Delay.