Design and Implementation of Hamming Code on FPGA using Verilog
Ravi Hosamani1, Ashwini S. Karne2
1Ravi Hosamani, Department of Electronics and Communication Engineering, VTU Belgaum, K.L.E. Institute of Technology, Hubli.
2Ashwini S. Karne, Department of Electronics and Communication Engineering, VTU Belgaum, K.L.E. Institute of Technology, Hubli.
Manuscript received on November 26, 2014. | Revised Manuscript received on December 09, 2014. | Manuscript published on December 30, 2014. | PP: 180-184 | Volume-4 Issue-2, December 2014. | Retrieval Number: B3676124214/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In mathematics, digital communication and information theory, error detection and correction has great practical importance in maintaining information integrity across noisy channels. Error coding is considered as a method of detecting and correcting these errors to ensure that the information is transferred intact from its source to its destination. There are various error correcting techniques to detect and correct the error. One of the popular technique based on forward error correction is Hamming Code. This paper focuses on design and its hardware implementation on Field programmable Gate Array(FPGA). The design includes both of the encoder and decoder systems to be used for the serial data transmission and reception of the wireless transceiver systems. The design has been simulated and verified using ISim simulator and Verilog HDL. Spartan-3 FPGA trainer kit for Xilinx 14.3 has been used for the implementation.
Keywords: Error coding, Hamming code, Encoder, Decoder, Verilog HDL, FPGA, Xilinx, Spartan 3.