Application of PODEM Algorithm for Fault Detection and Location in FinFet based Combinational VLSI Circuits
K.V.B.V Rayudu1, D R Jahagirdar2, P Srihari Rao3

1K.V.B.V Rayudu, Scientist ‘G’ Head, Reliability Engineering Division, Research Centre Imarat, Vignyanakancha Po, Hyderabad, India.
2D R Jahagirdar, Scientist ‘G’ Research Centre Imarat, Vignyana Kancha Po, Hyderabad, India.
3Dr P Srihari Rao, Associate Professor, NIT Warangal, Telangana, India.
Manuscript received on November 25, 2019. | Revised Manuscript received on December 08, 2019. | Manuscript published on December 30, 2019. | PP: 236-241 | Volume-9 Issue-2, December, 2019. | Retrieval Number: B3565129219/2019©BEIESP | DOI: 10.35940/ijeat.B3565.129219
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Abstract: Fin Fet transistors are used in major semiconductor organizations and a significant role is played by it in developing the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, different algorithms such as PODEM (Path Oriented Decision Making algorithms) are used to find the fault detection and location. The Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this research work Combinational Circuits are designed using 20nm/32nm technology nodes in LT Spice environment and PODEM Algorithm is implemented which is developed in MATLAB, to detect and identify fault location and sensitive test vector to detect fault in the circuit and results are presented.
Keywords: Fin Fet transistors, Fault analysis, Transfer characteristics. , PODEM Algorithm, Fault Diagnosis, Fault Detection.