Energy Efficient Adiabatic Full Adders for Future SOC’s
B. Sravan Kumar1, Rajeshwara Mahidhar.P2, N.V.G.Prasad3
1B.Sravan Kumar, M. Tech. Student, Department of ECE, Sasi Institute of Technology & Engineering College, Tadepalligudem (A.P.), India.
2Rajeshwara Mahidhar. P, Asst. Professor, Department of ECE, Sasi Institute of Technology & Engineering College, Tadepalligudem (A.P.), India.
3N.V.G. Prasad, Associate Professor & Head, Department of ECE, Sasi Institute of Technology &Engineering College, Tadepalligudem(A.P.), India.
Manuscript received on November 21, 2012. | Revised Manuscript received on December 09, 2012. | Manuscript published on December 30, 2012. | PP: 353-356 | Volume-2, Issue-2, December 2012. | Retrieval Number: B0965112212 /2012©BEIESP
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Abstract: In this paper we are going to compare the adiabatic logic designs & designing a new full adder using ECRL & PFAL logics after that the simulations were done using Micro wind & DSCH. Thus the efficiency of the circuits is shown & compared using different nano meter technologies.
Keywords: Adiabatic, ECRL, Adder, PFAL adder, Full adder, Low Power Adders.