Designing Of Reconfigurable MPNOC On FPGA For Processing The Wireless Sensor Networks
R.Ramachandran1, J. Thomas Joseph Prakash2
1R.Ramachandran, Research Scholar, Applied Electronics, Manonmaniam Sundaranar University, Tirunelveli, (Tamil Nadu), India.
2Dr. J. Thomas Joseph Prakash, Assistant Professor, Department of Physics, H.H. The Rajah’s College, Pudukkottai, (Tamil Nadu), India.
Manuscript received on October 28, 2012. | Revised Manuscript received on November 14, 2012. | Manuscript published on December 30, 2012. | PP: 13-19 | Volume-2, Issue-2, December 2012. | Retrieval Number: B0892112212 /2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Designing of system on chip with the current algorithm and design methodology cannot meet the requirements of accommodating billion-transistor area in VLSI technology. There is a need of plat form based design and computing system design. It is to implement FPGA based reconfigurable Multiple Processor Network on Chip (MPNOC) which consists of Multiple Processing Units (MPUs),Communication controller (CC) and Memory Units (MU). The processing units are System on Chips; they are communicated each and other or connected with Routers. In this work No C designed for processing the signals of wireless sensor networks, such as GPS, RF sensor, RFID, and Zigbee outputs. The proposed System was thus designed and simulated in ALTERA IDE’s platform. In this work, the SOPC Builder component editor has been used to configure the node elements and to create Custom network interface component. In order to implement the designed Noc in FPGA chip, Altera Quartus II CAD tool was used, which compiles HDL written for configuring NoC , also generates RTL View and timing analyzer for the main components.
Keywords: MP No C, SoC, Reconfigurable Network on Chip, Wireless system, WSN.