Pulsating STM – The in-memory Optimistic Concurrency Control Technique for Multi Core Systems
Sana Jafar1, Ranjana Rajnish2, Pankaj Kumar3
1Sana Jafar*, Amity Institute of Information Technology, Amity University Uttar Pradesh, Lucknow Campus, Lucknow(India), India.
2Ranjana Rajnish, Amity Institute of Information Technology, Amity University Uttar Pradesh, Lucknow Campus, Lucknow(India), India.
3Pankaj Kumar, Department of Computer Science and Engineering, Sri Ram Swaroop College of Engineering and Management, Lucknow, India.
Manuscript received on September 22, 2019. | Revised Manuscript received on October 20, 2019. | Manuscript published on October 30, 2019. | PP: 1966-1972 | Volume-9 Issue-1, October 2019 | Retrieval Number: A9525109119/2019©BEIESP | DOI: 10.35940/ijeat.A9525.109119
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Abstract: In the world of ever increasing parallelism, the problem of deadlock-free concurrency control is inevitable. As the number of processing cores is increasing, the number of processing threads is also increasing, and with this increase in the number of processing threads, there is a good chance of problems arising due to lack of proper concurrency control. The application areas under the domain of advanced graphics, cryptography, deep learning, embedded system programming, artificial intelligence and networking are prone to the problems of heavy uncontrolled concurrency of threads. This paper presents a novel Software Transactional Memory (STM) based optimistic concurrency control technique that is deadlock free for threads accessing the in-memory data structure for the purpose of reading as well as writing. The technique is lock free and is based upon timestamping. Threads involved in the proposed approach possess the transactional properties of atomicity, concurrency and isolation. Durability is not expected as the threads are working on an in-memory data source. The approach involves lazy conflict detection that ensures minimum aborts and restarts as well as maximum concurrency among transactions. Being lock free, the algorithm is better than the existing lock-based techniques. The technique is tested on Sniper-6.1 multi core simulator simulating 64 CPU cores and running 16, 32, 40 and 50 threads in our case. The results show significant improvement in throughput with the increasing number of threads over the existing lock-based techniques as well as other STM techniques based on optimistic concurrency control.
Keywords: Concurrency Control, Optimistic Concurrency control, multi core, Software Transactional Memory, parallel programming, in-memory data structure, Sniper multi core simulator, Cycles Per Instructions.