Efficient Communication in any Digital System using Convolutional Encoder and Viterbi Decoder for Constraint Length 9
B. Pullaiah1, M. Sailaja2
1B. Pullaiah, Department of Instrumentation and Control Systems, M. Tech, Jawaharlal Nehru Technological University, Kakinada, India.
2Dr. M. Sailaja, Prof. Department of ECE, Jawaharlal Nehru Technological University, Kakinada, India.
Manuscript received on September 30, 2014. | Revised Manuscript received on October 16, 2014. | Manuscript published on October 30, 2014. | PP: 217-220 | Volume-4 Issue-1, October 2014. | Retrieval Number: A3545104114/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Forward Error Correction (FEC) schemes are an essential component of wireless communication systems. Present wireless standards such as Third generation (3G) systems, GSM, 802.11A, 802.16 utilize some configuration of convolutional coding. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. The Viterbi algorithm is the most extensively employed decoding algorithm for convolutional codes which comprises of minimum path and value calculation and retracing the path. The efficiency of error detection and correction increases with constraint length. In this paper the convolutional encoder and viterbi decoder are implemented on FPGA for constraint length of 9 and bit rate ½.
Keywords: Constraint length, Convolutional encoder, forward error correction, FPGA and viterbi decoder.