Parallel CRC Generation for High Speed Applications
B. Naveen1, K. Swaraja2, M. C. P Jagdissh3
1B. Naveen, ECE Dept, MREC, Secunderabad, India.
2K. Swaraja, ECE Dept, MREC, Secunderabad, India.
3Dr. M. C. P Jagdissh, HOD, ECE Dept, MREC, Secunderabad, India.
Manuscript received on September 26, 2013. | Revised Manuscript received on October 12, 2013. | Manuscript published on October 30, 2013. | PP: 429-431  | Volume-3, Issue-1, October 2013. | Retrieval Number:  A2311103113/2013©BEIESP

Open Access | Ethics and Policies | Cite
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (

Abstract: Cyclic redundancy check is commonly used in data communication and other fields such as data storage and data compression, as a essential method for dealing with data errors. Usually, the hardware implementation of CRC computations is based on the linear feedback shift registers (LFSRs), which handle the data in a serial way only, Though the serial calculation of the CRC codes cannot achieve a high throughput. parallel CRC calculation can significantly increase the throughput of CRC computations. Variants of CRCs are used in applications like CRC-16 BISYNC protocols, CRC32 bit in Ethernet frame for error detection, CRC8 bit in ATM, CRC-CCITT in X-25 protocol, disc storage, SDLC, and XMODEM. High speed data transmission is the current scenario in networking environment. Cyclic redundancy check (CRC) is essential method for detecting error when the data is transmitted. About the speed of transmitting data, and to synchronize with speed, it is necessary to increase speed of CRC generation. Starting from the serial architecture a recursive formula was used from which parallel design is obtained. But in this paper presents 64 bits parallel CRC architecture based on F matrix with order of generator polynomial is 32. It is hardware efficient and required 50% less cycles to generate CRC with same order of generator polynomial. In this architecture w= 64 (input) bits are parallel processed and order of generator polynomial is m= 32. If 32 bits are processed parallely then CRC-32 will be generated after (k +m)/w cycles. Where ‘k’ indicates number of data bit and ‘m’ indicates the order of generator polynomial If we increase number of bits to be processed parallely, number of cycles required to calculate CRC can be reduced.
Keywords: Cyclic Redundancy Check, Parallel CRC calculation, Linear Feedback Shift Register, LFSR, F matrix.