Hardware Implementation of Involutional SPN Block Ciphers
Rakhesh Kusagur1, Leelavathi G.2
1Mr. Rakhesh  Kusagur, VLSI Design and Embedded Systems, VTU Extension Center, UTL Technologies, Bangalore, India.
2Mrs. Leelavathi G, VLSI Design and Embedded Systems, VTU Extension Center, UTL Technologies, Bangalore, India.
Manuscript received on September 27, 2013. | Revised Manuscript received on October 03, 2013. | Manuscript published on October 30, 2013. | PP: 418-421  | Volume-3, Issue-1, October 2013. | Retrieval Number:  A2278103113/2013©BEIESP

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Consider the two involutional SPN (substitution-permutation network) block ciphers, namely KHAZAD and BSPN, since both of these algorithms adopt SPN structure. Investigation of the energy cost of the FPGA implementation of these two cryptographic algorithms targeted to wireless sensor networks (WSNs) has to be done. Recent trends have seen the emergence of WSNs using sensor nodes based on reprogrammable hardware, such as a field-programmable gate arrays (FPGAs), thereby providing flexible functionality with higher performance and speed than classical microcontroller based sensor nodes. Investigation of the hardware implementation of involutional SPN block ciphers has to be carried out since the characteristics of involution enables performing encryption and decryption using the same circuit. This characteristic is particularly suitable for a wireless sensor node which requires the function of both encryption and decryption. Further, in order to consider the suitability of a block cipher for some of the applications like wireless sensor node, it is most critical to consider the cost of encryption in terms of energy consumption because wireless sensor node is a energy constrained device. Hence, it is appropriate to chose two involutional SPN block ciphers namely KHAZAD and BSPN and analyze their energy efficiency for implementation in the FPGA.
Keywords: Security, Block ciphers, Field Programmable gate arrays, Involutional.