FIR Filter Design using Finfets at 22nm Technology
N. Praveen Kumar1, B. Stephen Charles2, V.Sumalatha3

1N. Praveen Kumar*, ECE Department, JNTUA University, Kurnool, India.
2Dr. B. Stephen Charles, Principal, Stanley Stephen College of Engg & Tech, Kurnool, India.
3Dr. V. Sumalatha, Professor, JNTUA University, Anantapur, India.
Manuscript received on November 20, 2019. | Revised Manuscript received on December 15, 2019. | Manuscript published on December 30, 2019. | PP: 1292-1295 | Volume-9 Issue-2, December, 2019. | Retrieval Number:  A2018109119/2020©BEIESP | DOI: 10.35940/ijeat.A2018.129219
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Abstract: Finite Impulse Response (FIR) filters are the most significantdevice in digital signal processing. In many Digital Signal Processing applications like wireless communication, image and video processing FIR filters are used. Digital FIR filters primarily consists of multipliers, adders and delay elements. Area, power optimization and speed are the key design metrics of FiniteImpulse Response filter. As more electronic devices are battery operated, power consumption constraint becomes a major issue. Multipliers are the core of FIR filters. They consume a lot of energy and are generally complex circuits. With each new process technologies, the short channel effects limit the performance of FIR filters at nano regime. Various architectures have been proposed to enhance the performance of FIR filter. In this paper, FIR filter is designed using FINFETs at 22nm technology using Hspice software.
Keywords: FIR, SCE, FINFETs.