The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology
Chaitanya Kommu1, A Daisy Rani2

1Chaitanya Kommu*, Instrument Technology, Andhra University, Visakhapatnam, India.
2Dr. A daisy Rani, Instrument Technology, Andhra University, Visakhapatnam, India.
Manuscript received on September 16, 2019. | Revised Manuscript received on October 20, 2019. | Manuscript published on October 30, 2019. | PP: 43-49 | Volume-9 Issue-1, October 2019 | Retrieval Number: A1027109119/2019©BEIESP | DOI: 10.35940/ijeat.A1027.109119
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Abstract: Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors.
Keywords: Low power CMOS, Pass transistors, Skew gates Transmission gate.