A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator
Nadendla Bindu Priya1, Muralidharan Jayabhalan2
1Nadendla Bindu Priya, Department of ECE, VFSTR Guntur (Andhra Pradesh), India.
2Muralidharan Jayabhalan, Assoiate Professor, Department of ECE, VFST Guntur (Andhra Pradesh), India.
Manuscript received on 23 November 2019 | Revised Manuscript received on 17 December 2019 | Manuscript Published on 30 December 2019 | PP: 41-44 | Volume-9 Issue-1S5 December 2019 | Retrieval Number: A10121291S52019/19©BEIESP | DOI: 10.35940/ijeat.A1012.1291S52019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5- bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5- bit ADC operates voltage at 1.8 volts and consumes an average power.
Keywords: Pseudo NMOS, Strong Arm Comparator, Asynchronous Digital Slope Analog To Digital Converter (ADS ADC)
Scope of the Article: Digital Signal Processing Theory