Emulator for FPGA based RADAR signal Processing
C.Thippeswamy1, J. Chinna Babu2, K.Padmapriyat3
1C.Thippeswamy, ECE AITS, Rajampet, JNTU Anantapur, (A.P), India.
2Mr. J. Chinna Babu, Assistant Professor Department of ECE, AITS, Rajampet, JNTU Anantapur, (A.P), India.
3Dr. K. Padmapriya, JNTUCE, Anantapur, (A.P), India.
Manuscript received on September 21, 2012. | Revised Manuscript received on October 15, 2012. | Manuscript published on October 30, 2012. | PP: 275-278 | Volume-2 Issue-1, October 2012.  | Retrieval Number: A0791102112 /2012©BEIESP

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Abstract: The present day RADARs use complex schemes such as stagger PRI, jitter PRI along with frequency agile characteris-tics. The frequency agile RADARs switch frequencies with in a pulse to get different types of advantages. Today lot of RADAR (Radio Detection and Ranging) signal processing takes place on FPGA(Field Programming Gate Array) platform. Th-se signal processing algor-thms include pulse parameters estimation, dei nt-erleaving of mixed pulse patterns, processing complex chirp signals etc. All these algorithms need to be tested at various levels before they get integrated in to final system. However today no technique or solution available by which, these algoritms can be tested on FPGA with realistic signals. In this project a RADAR signal emulator will be built which can generate the samples even corresponding to multiple complex RADARs at a time. Since FPGA is a parallel platform this emulation is possible. The complete project development consists of mainly two modules, the scenario creator and control logic. The control logic communicates with PC using serial port to capture the parameters set by the user in PC. These parameters are loaded into respective source simulator modules. Each source simulator module consists of NCO for digital carrier generation and pulse modulator. The NCO is programmable to generate all types of frequency agile signals in real time. A top level module consists of all these blocks and will be synthesized to Xilinx FPGAs. The final FPGA output will be demonstrated in real-time with Chip scope. 
Keywords: RADAR,FPGA, PRI, Jitter PRI, Emulator.