Design and Implementation of Low-Power High-Performance Carry Skip Adder
Santanu Maity1, Bishnu Prasad De2, Aditya Kr. Singh3
1Santanu Maity, M.Tech, VLSI Design and Microelectronics from Haldia Institute of Technology, Haldia, India.
2Bishnu Prasad, Department of Electronics and Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
3Aditya Singh M.tech in VLSI Design and Microelectronics from Haldia Institute of Technology, Haldia, India.
Manuscript received on March 02, 2012. | Revised Manuscript received on March 31, 2012. | Manuscript published on April 30, 2012. | PP: 212-218 | Volume-1 Issue-4, April 2012 | Retrieval Number: D0319041412/2012©BEIESP
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Abstract: The most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved. In VLSI applications, area, delay and power are the important factors which must be taken into account in the design of a fast adder. The carry-skip adder reduces the time needed to propagate the carry by skipping over groups of consecutive adder stages, is known to be comparable in speed to the carry look-ahead technique while it uses less logic area and less power. In this paper, a design of 8-bit Carry Skip Adder by various existing logic styles are to be compared quantitatively and qualitatively by performing detailed transistor-level simulation using T-Spice v13.0.
Keywords: Low power, High performance, Carry Skip adder, Logic design style, CMOS, CPL, DPL, Reversible Logic.