Design of 10 Bit ADC of SAR Type to Increase the Accuracy for Biomedical Applications
Amrita Sajja1, S. Rooban2
1Amrita Sajja, Research Scholar, Department of ECE,Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, A.P. India.
2S. Rooban, Associate Professor, Department of ECE,Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, A.P. India.
Manuscript received on January 26, 2020. | Revised Manuscript received on February 05, 2020. | Manuscript published on February 30, 2020. | PP: 2291-2294 | Volume-9 Issue-3, February 2020. | Retrieval Number: C5309029320/2020©BEIESP | DOI: 10.35940/ijeat.C5309.029320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper a low power consuming 10 bit SAR ADC which is suitable for Biomedical applications is presented. It was designed with 180nm technology using cadence tool. SAR ADC is made of dynamic comparator, sample and hold circuit, SAR logic, and DAC block. The designed circuit works on a supply voltage of 1V. The proposed SAR design, with the use of dynamic comparator circuit will help to reduce power and even at the same time with the use of binary weighted CDAC also provides low power dissipation. In order to decide the next significant bit by the knowledge of previous bits the successive approximation algorithm runs over several clock cycles for analog to digital conversion. Power usage and complexity of the circuit is minimized by low conversion rate i.e permitting one clock for each bit in the proposed method.
Keywords: SAR [Successive Approximation Register] , low supply voltage, CDAC (capacitive digital to analog converter), low power.