Low Power and High Speed Synchronous Carry Generate Adder using Modified Gate Diffusion Input Technique
P. Kishore1, S. Rajendra Prasad2, Y. Chalapathi Rao3
1P.Kishore, Assistant Professor, Department of ECE, VNR VJIET, Hyderabad (Telangana), India.
2S.Rajendra Prasad, Professor, Department of ECE, VNR VJIET, Hyderabad (Telangana), India.
3Y.Chalapathi Rao, Associate Professor, Department of ECE, VNR VJIET, Hyderabad (Telangana), India.
Manuscript received on 22 April 2019 | Revised Manuscript received on 01 May 2019 | Manuscript Published on 05 May 2019 | PP: 192-196 | Volume-8 Issue-2S2, May 2019 | Retrieval Number: B10410182S219/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Low power and high performance designs drew major focus in digital VLSI. In low-voltage and low-power applications, optimization of power dissipation and propagation delay of logic circuits is an important issue. Now a days, most of the high performance processors are built with arithmetic logic units in which the adders and multipliers are key components. The efficiency of these processors will be measured in terms of power dissipation, speed of operation. So, in order to develop low power and high performance processors, it is necessary to design the multipliers and adder circuits with required speed and power dissipation. This paper concentrates on design of a synchronous carry generate adder, generally called carry Look-ahead adder with low power dissipation and less propagation delay. The proposed design is implemented using a Modified Gate Diffusion Input technique in mentor graphics tools at 90nm technology.
Keywords: Power Dissipation, Propagation Delay, GDI Technique, Carry Look-Ahead Adder.
Scope of the Article: High Speed Networks