Xilinx Based Electronic Voting Machine
K. Gurucharan1, B. Kiranmai2, S. S. Kiran3, M. Ravindra Kumar4
1Mr. K. Gurucharan*, Dept. of Electronics and Communication Engineering, Sanketika Institute of Technology and Management, Visakhapatnam, India.
2Dr. B.Kiranmai, Dept. of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.
3Mr. S S Kiran, Dept. of. Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.
4Mr. M Ravindra Kumar, Dept. of. Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, India.
Manuscript received on September 17, 2019. | Revised Manuscript received on October 15, 2019. | Manuscript published on October 30, 2019. | PP: 3935-3939 | Volume-9 Issue-1, October 2019 | Retrieval Number: A1484109119/2019©BEIESP | DOI: 10.35940/ijeat.A1484.109119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Conventional paper based voting procedure was terribly long process and extremely prone to errors. Polling by Electronic Voting Machine (EVM) is easy, safe and secure methodology that takes minimum of our time .In order to perform this mechanism, there were several phases in the design process such as designing a flow chart, algorithm and simultaneously the code is developed to implement & stimulate the logic. The proposed digital EVM was designed on Xilinx ISE using verilog HDL and can also be implemented on FPGA board for real time purpose. The proposed method consists of 3 stages, in the first stage we decide the total no. of voters and the total number of contestants taking part in the election process .we have assigned Voting enable which is active high input signal for the voter in order to cast his vote by using voter switch input signal for making this election process more secure and safe. In stage two, voting process begins when the voter casts his vote to a particular party or contestants the polled vote is registered in the individual contestant registry. In stage three after completion of voting process the votes are validated by comparing the votes polled to the contestants in their registries after which the election process ends by declaring the winner. The above proposed method can be implemented on FPGA board for real time applications ranging from university level elections to Assembly and Lok Sabha elections, as it has the advantage that it can be reprogrammed over and over for various tasks according to their requirement which helps in reducing the expenditure.
Keywords: HDL, XILINX, EVM, FPGA.