Architectural Enhancement of Network on Chip
Senthil Athiban M1, Mehazin Shaju2, M M Sravani3, S Ananiah Durai4
1Senthil Athiban, Pursuing Master of Science, Department of Electrical Engineering, Specializing, Electronics and Mixed Signal Circuits Arizona State University, United States, America.
2Mehazin Shaju Research and Development Engineer, Continental, Bengaluru (Karnataka), India.
3Sravini Pursuing Ph.D Under, Dr. S Ananiah Durai, Vellore Institute of Technology, Chennai (Tamil Nadu), India.
4Dr. S Ananiah Durai, Associate Professor, Department of Electronics Engineering, Vellore Institute of Technology, Chennai (Tamil Nadu), India.
Manuscript received on 16 December 2019 | Revised Manuscript received on 23 December 2019 | Manuscript Published on 31 December 2019 | PP: 287-290 | Volume-9 Issue-1S3 December 2019 | Retrieval Number: A10541291S319/19©BEIESP | DOI: 10.35940/ijeat.A1054.1291S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper gives a new architectural design suggestion of NoC, with efficient way of communication. Firstly, to create a serial data communication architecture in competence with the existing widely used parallel form of data transmission and reception . Secondly to enable simultaneous transmission and reception between more than one module at the same time. Thirdly to create the architecture that is modifiable as per the need of user. The theoretical data rate calculated was 300 MBps. The throughput we achieved after the completion is 250MBps.
Keywords: Architecture, NoC, SoC, Topology.
Scope of the Article: Foundations of Communication Networks