Design of Low Power Hybrid Gaincell-e DRAM for Embedded Processors
G Vamsi Krishna Reddy1, Sri. G. Ramesh2
1G Vamsi Krishna Reddy*, Pursuing M. Tech in VLSI and ES at G. Pulla Reddy College of Engineering, Kurnool, (Andhra Pradesh), India.
2G. Ramesh, Assistant Professor, Department of Electronics and Communication Engineering, G. Pulla Reddy College of Engineering, Kurnool, (Andhra Pradesh), India.
Manuscript received on July 11, 2019. | Revised Manuscript received on August 13, 2019. | Manuscript published on August 30, 2019. | PP: 4731-4733 | Volume-8 Issue-6, August 2019. | Retrieval Number: F9227088619/2019©BEIESP | DOI: 10.35940/ijeat.F9227.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This brief mainly focuses on increasing the data retaining capability at the Storage Node (SN) and reducing the power consumed by the Hybrid Gaincell eDRAM SRAM (HGC-eDRAM SRAM). A Hybrid Gaincell eDRAM SRAM cell contain SRAM cell and DRAM cell. Both the SRAM and DRAM cell share the SN. The DRAM cell here is implemented as 3T Gaincell. The data retaining capability is improved by isolating the shared SN of the SRAM cell and adding a capacitance at the SN if the 3TGaincell. The above-mentioned modifications are implemented in Cadence Virtuoso 6.1.6 using 90nm technology.
Keywords: Gaincell, SRAM, Embedded DRAM (eDRAM), Hybrid gaincell.