Effective Usage of Chip Area by Optimizing the Dead Space
Ganugaphati Venkata Sai Mohan1, Venkat Rao Ganjanaboyina2

1Ganugaphati Venkata Sai Mohan*, Electronics and Communication Engineering, Laki Reddy Bali Reddy College of Engineering, Mylavaram, India.
2Venkat Rao Ganjanaboyina, Assistant Professor, Electronics and Communication Engineering , LakiReddy Bali Reddy College of Engineering, Mylavaram, India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 2601-2603 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8753088619/2019©BEIESP | DOI: 10.35940/ijeat.F8753.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In the modern VLSI (Very Large Scale Integration) physical design, floor plan is the main step to optimize the circuit. The objective of floor plan is to optimize the interconnection between modules, area optimization and minimize the dead space. For very deep micron technologies, one of the major issue to design an chip is Dead space in physical design. In this paper, we introduced an algorithm for reducing dead space. This algorithm wrote in tickel programming language and implemented in Cadence Innovas Encounter Tool. By comparing to default algorithm floor plan, this algorithm reduces more dead space in the floor plan stage of the design.
Keywords: VLSI , Floor plan , Dead space, physical design.