Implementation of Word Level Parallel Processing Unfolding Algorithm using VHDL
Manoj Kumar1, Karni Ram2

1Dr. Manoj Kumar, Department of ECE, NIT Manipur, Imphal , India.
2Karni Ram, Department of ECE, NIT Manipur, Imphal , India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 664-667 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8099088619/2019©BEIESP | DOI: 10.35940/ijeat.F8099.088619
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Abstract: Aim of this paper is to apply the unfolding algorithm to FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) filter and compare with original filter and parallel processing filters architecture. FIR filter and IIR filter are implemented by using VHDL (Very High Speed Integrated Circuit Hardware Description Language).In this paper, 2-parallel processing and 3-parallel processing of FIR and IIR filter are implemented and FIR and IIR filter are also implemented with unfolding factor 2 and unfolding factor 3 using VHDL. The simulation is done on Artix-7 series FPGA, target device (xc7a200tfbg676) (speed grade -1) using VIVADO 2016.3. Implemented design works on 1200 KH z clock whereas parallel inputs are generated on 3600 KH z clock. The proposed technique reduces the critical path delay in comparison with existing literature. Also, the experimental result shows that the speed for 3-unfolded IIR filter is more than 3-parallel IIR filter.
Keywords: DSP, FIR, FPGA, IIR, VHDL.